In applications of large scale integrations (LSIs), static random access memories (SRAMs) are the widely-used on-chip memories. Unlike dynamic random access memories (DRAMs), an SRAM only needs to be powered to store data, and does not necessarily need to be refreshed. Therefore, SRAMs may have advantages including high speed and low power consumption, etc.
FIG. 1 illustrates a circuit structure of an existing SRAM, which may have six transistors (6T SRAM). As shown in FIG. 1, the 6T SRAM may include a first pull-up PMOS transistor PU1, a second pull-up PMOS transistor PU2, a first pull-down NMOS transistor PD1 and a second pull-down NMOS transistor PD2. Sources of the first pull-up PMOS transistor PU1 and the second pull-up PMOS transistor PU2 may connect with a power source Vdd. Sources of the first pull-down NMOS transistor PD1 and the second pull-down NMOS transistor PD2 may connect with a ground Vss. The first pull-up PMOS transistor PU1 and the first pull-down NMOS transistor PD1 may form a first inverter. The second pull-up PMOS transistor PU2 and the second pull-down NMOS transistor PD2 may form a second inverter. The output of the first inverter may electrically connect with the input of the second inverter, and a first storage node Q may be formed. The input of the second inverter may electrically connect with the output of the first inverter, and a second storage node QN may be formed.
Because the first inverter and the second inverter may have a cross-coupling effect, a latch circuit may be formed. When one storage node is pulled down to a lower potential, the other storage node may be pulled up to a higher potential. The first storage node Q may connect with a first transfer gate TG1. The second storage node QN may connect with a second transfer gate TG2. The first transfer gate TG1 and the second transfer gate TG2 may connect with a first word line WL1.
When the first word line WL1 is switched to a system high potential, the first transfer gate TG1 and the second transfer gate TG2 may be turned on, and a first bit line BL1 and a second bit line BL2 may be allowed to write data into the first storage node Q and the second storage node QN, or to read data from the first storage node Q and the second storage node QN. When the first word line WL1 is switched to a system low potential, the first transfer gate TG1 and the second transfer gate TG2 may be turned off, the first bit line BL1 and the second bit line BL2 may be isolated from the first storage node Q and the second storage node QN.
However, the existing 6T STRAM structure may perform a data reading and a data writing by the first transfer gate TG1 and the second transfer gate TG2, which may cause the existing 6T SRAM to perform only one operation of the data reading and the data writing in one time sequence, it may be impossible to perform a data reading and a data writing simultaneously. Thus, the 6T SRAM may have a relatively low data reading and writing speed.
Therefore, in order to increase the data reading and data writing speed, dual-port SRAMs have been developed. Referring to FIG. 1, the dual port SRAM may be formed by adding a third transfer gate TG3 and a fourth transfer gate TG4 to the existing 6T SRAM, an 8T SRAM may be formed. The third transfer gate TG3 and the fourth transfer gate TG4 may connect with the first storage node Q and the second storage node QN. The third transfer gate TG3 and the fourth transfer gate TG4 may also connect with a second word line WL2.
When the second word line WL2 is switched to a system high potential, the third transfer gate TG3 and the fourth transfer gate TG4 may be turned on, and the third transfer gate TG3 and the fourth transfer gate TG4 may be used to read data from the first storage node Q and the second storage node QN, or write date to the first storage node Q and the second storage node QN by a third bit line BL3 and a fourth bit line BL4. When the second word line WL2 is switched to a system low potential, the third transfer gate TG3 and the fourth transfer gate TG4 may be turned off, the third bit line BL3 and the fourth bit line BL4 may be isolated from the first storage node Q and the second storage node QN. After adding the third transfer gate TG3 and the fourth transfer gate TG4, the dual-port SRAM may perform a data reading and a data writing by the first word line WL1 and the second word line WL2 simultaneously, the data reading and writing rate of the SRAM may be significantly increased.
However, the data writing and data reading of existing dual-port SRAMs may be unstable. The disclosed device structures and systems are directed to solve one or more problems set forth above and other problems.